The invention relates to electronic devices, and, more particularly, to digital communications and storage with partial response sequential detectors.
FIG. 1a schematically illustrates a magnetic storage and retrieval system. In particular, writing data bits to storage on magnetic disk 111 proceeds as follows. Error correction coder 101 encodes data bits into error corrected bits by an error correction encoding method such as Reed-Solomon. Further, the error correction coding may include interleaving of blocks of bits. Next, modulation coder (channel coder) 103 codes blocks of bits output by error corrected coder 101 into blocks of bits using a runlength-limited code or other channel code which may include a parity bit for post processing removal of dominant errors. This modulation coding helps read timing recovery. These blocks may then be precoded. Then the (precoded) modulation coded bits drive the read/write head to set the magnetization orientation of domains on spinning magnetic disk 111; this stores the data bits.
The reading of the stored data bits first amplifies (and filters) with amplifier 121 voltages induced in the read/write head 113 due to the transitions of magnetization orientation of domains on spinning disk 111. These voltages have the ideal form of a sequence of overlapping pulses, such as illustrated (after shape filtering) in FIGS. 2a-2c, with positive, negative, or zero amplitudes. The pulse overlaps imply intersymbol interference if the subsequent digital sampling includes contributions from more than one pulse; indeed, FIGS. 2a-2c indicate the ideal sampling times. Clocked analog-to-digital converter 123 samples and quantizes the sequence of pulses to form a digital output stream; there may be 64 or 128 quantization levels (a 6-bit or 7-bit converter with one sign bit and 5 or 6 magnitude bits). The Viterbi detector 125 performs a maximum likelihood data detection on the digital output stream.
For partial response signaling various classes of frequency response for the signal channel prior to detection have been defined; and the class IV response appears particularly suitable for magnetic recording due to pulse shapes requiring minimal equalization. The partial response class IV channel is defined by a channel transfer function polynomial of the form (1xe2x88x92D)(1+D)N where N is a positive integer and D is a one period delay. FIGS. 2a-2c shows the pulse shapes for N=1, 2, and 3; the corresponding pulses are termed PR4, EPR4, and E2PR4 (or EEPR4), respectively. Thus an (E)PR4 sensed voltage consists of a sequence of overlapping (E)PR4 pulses spaced one period apart and with positive, negative, or zero amplitudes depending upon the corresponding transitions of magnetization domain orientations. The sampling of the (E)PR4 sensed voltage yields the digital stream input to the detector, typically a sequence detector such as a maximum likelihood Viterbi decoder. Higher storage densities on a magnetic disk require more samples per induced pulse and consequent more overlap, and thus the higher order polynomial transfer functions are used. For example, storage densities of about 3 bits per PW50 (pulse width at half maximum amplitude) would use EEPR4 which has four nonzero samples per pulse; see FIG. 2c. The demand for high density originates with small, portable devices such as notebook computers.
Modulation decoder 127 is the inverse of modulation coder 103. Lastly, error correction decoder 129 deinterleaves and further corrects errors and recovers the data bits, hopefully with only minimal errors.
Maximum likelihood detection of a digital stream with intersymbol interference can be described in terms of maximizing probabilities of paths through a trellis of state transitions (branches); each state corresponds to a possible pattern of recently received data bits and each stage of the trellis corresponds to a receipt of the next (noisy) input. For example, FIG. 3 illustrates one stage (one step in time) in the trellis for an EPR4 detector; the states are labeled with three previous data bits (reflecting the three non-zero sampled values in the isolated pulse) and the branches are labeled with the bit for the branch transition plus the corresponding noiseless input sample target values: 2, 1, 0, xe2x88x921, or xe2x88x922.
FIG. 4 shows a prior art Viterbi detector which includes one add-compare-select (ACS) unit for each trellis state and a branch metric unit for each of the target levels tij; the survival register for each state is in the path memories block. Each branch metric unit computes the square of the difference between its target value and the noisy input sample value. Each ACS stores a metric for its state and has inputs for the appropriate branch metric computations and the related state metrics from other ACS units. At receipt of an input signal to the detector, each ACS adds its (two) input branch metric computations to the corresponding state metrics of the states emitting the branches; and then it compares these (two) sums and selects the smaller as the updated state metric for its state. Each state""s survival register updates its contents to maintain a survival path for the state; that is, the sequence of selected bits (transitions) that have led to the updated state metric. The detected bits will correspond to the path with the smallest metric. At any time the maximum likelihood path through the trellis up to that time is the path traced backwards through the trellis starting from the state with the smallest state metric at that time and recursively using the branch previously selected as the branch into the traced-to state. That is, the survival register contents for the state with the smallest state metric.
The length of the survival registers depends on the modulation code used. As the decision goes deeper into the survival registers, more of the contesting survival paths (versus the correct path) will be eliminated, the detected data will become more accurate.
To further improve the performance of (E)PR4 channels, modulation codes have been proposed which add code constraints to eliminate the most common error events. An error event metric may be defined as the difference between the path metric for the correct path and path metric for the contender error path through the trellis that diverges from the correct path and later remerges. In EPR4 channels the minimum squared Euclidean distance (metric) between paths equals 4. The following pairs of bit sequences have trellis paths with this minimum error event metric:
The first four errors have a common characteristic in that the error occurs when three or more consecutive transitions exist. Thus a modulation code which prevents three consecutive transitions (NRZI tribits) will preclude the foregoing errors except for the single bit error. However, removing all tribits yields a low code rate. Consequently, various codes such as W.Bliss, An 8/9 Rate Time-Varying Trellis code for High Density Magnetic Recording, Proc. 1997 IEEE Int. Mag. Conf. (April 1997) remove quadbits and limit tribits to certain positions within the codeword to regain code rate.
But the problem of suppression of single bit errors persists. One approach adds a parity bit to codewords, but this lowers the code rate.
The present invention provides a device and method of single bit error suppression by post processing after Viterbi detection using a filtering of the difference of the ideal samples from the detected bit stream and the detector input sample stream.
This has the advantages of increased accuracy with limited additional post processing.